The AD9269 incorporates an optional integrated dc correction and quadrature
error correction block (QEC) that corrects for dc offset, gain, and phase
mismatch between the two channels. This functional block can be very beneficial
to complex signal processing applications such as direct conversion receivers.
The ADC also contains several features designed to maximize flexibility and
minimize system cost, such as programmable clock and data alignment and
programmable digital test pattern generation. The available digital test
patterns include built-in deterministic and pseudorandom patterns, along with
custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles. An
optional duty cycle stabilizer (DCS) compensates for wide variations in the
clock duty cycle while maintaining excellent overall ADC performance. The
digital output data is presented in offset binary, gray code, or twos complement
format. A data output clock (DCO) is pro-vided for each ADC channel to ensure
proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are
supported, and output data can be multiplexed onto a single output bus.
The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified
over the industrial temperature range (−40°C to +85°C).
- Diversity radio systems
- Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
- I/Q demodulation systems
- Smart antenna systems
- Battery-powered instruments
- Hand held scope meters
- Portable medical imaging
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